1. Field of the Invention
The present invention generally relates to microprocessors, such as those used by computer systems, and more particularly to a method of generating control signals for data flow in a single chip microprocessor.
2. Description of the Related Art
Microprocessors are used in a wide variety of electronic devices, from simple accessories such as wristwatches to more complicated computer systems. A typical microprocessor operates on input binary data to produce output binary data, according to various processor instructions. Even complicated functions can be broken down into a series of these simpler instructions. In other words, a program running on the microprocessor presents two kinds of values to the microprocessor, data and instructions. These values may originate from, e.g., program files stored on a permanent (non-volatile) medium provided with the microprocessor, such as a hard disk drive in a computer system, or from a temporary (volatile) storage device such as random-access memory (RAM) which has stored new data or instructions as a result of previous program execution. The values can also originate from a read-only memory (ROM) device, such as firmware which is used to initialize (boot) a computer when power is first turned on, or from an operator input device like a keyboard.
The physical embodiment of conventionally structured microprocessors is accordingly divided into two portions, a first dataflow portion composed of, e.g., adders, shifters and operand register files, and a second control portion which generates logical signals based on the instructions, that tell the dataflow portion where to get operands, what operation to perform, where to store the result, etc. The signals generated by the control portion are coupled to the dataflow portion as multiplexor gating signals, function control gates, etc., hereinafter collectively referred to as control signals.
FIG. 1 depicts the data flow for a conventional scalar microprocessor. The microprocessor includes a PC/Branch unit 10 which is connected to the remaining components shown in FIG. 1, including an instruction cache 12, an instruction buffer register 14, a register file 16, an execution-unit 18, an execution-unit (E-unit) operand multiplexor 20, a data cache 22, a data-cache (D-cache) data multiplexor 24, and an address multiplexor 26. PC/Branch unit 10 is controlled by two control signals, a branch operand source control signal 28 and a branch unit operation control signal 30. E-unit operand multiplexor 20 is controlled by an E-unit operand source control signal 32, while D-cache data multiplexor 24 is controlled by a D-cache data source control signal 34 and address multiplexor 26 is controlled by a D-cache address source control signal 36. Execution unit 18 is controlled by an E-unit operation control signal 38, and data cache 22 is controlled by a D-cache operation control signal 40.
An address which is supplied by PC/Branch unit 10 is used to access instruction cache 12 during a first cycle (cycle 1). The instruction which is associated with the address is latched into instruction buffer register 14 at the beginning of the second cycle (cycle 2). During cycle 2, control signals must be generated for branch unit 10, and the operand source controls for the various data and address multiplexors generated. The generation of the operand source controls is complicated by the possibility of data forwarding being necessary, e.g., an operand which has just been read from D-cache 22 is needed on the same cycle as it is being written into register file 16. In such a case, the operand multiplexor must be selected to take the operand from D-cache 22 and not from register file 16. During the third cycle (cycle 3), the function controls for data cache 22 and execution unit 18 must be available. During the last cycle (cycle 4), any result is written to register file 16.
The generation of microprocessor control signals (such as the signals 28 through 40) is conventionally performed in one of two well-known ways. The most common technique uses conventional logic circuits to implement boolean equations corresponding to the control signals. These conventional logic circuits may include AND/OR/INVERT gates (or any other complete logic family such as NOR, NAND, etc.) or array logic structures such as programmable logic arrays (PLAs). An alternative technique is to generate the control signals for the microprocessor through the use of horizontal microcode routines stored in a ROM or RAM array. This latter technique is usually used only when the microprocessor executes complex instructions taking several cycles.
There are still several limitations or disadvantages with the foregoing approaches for providing control signals. Considerable space must be provided on the microprocessor chip to allow the generation of control signals for a large number of instruction code points. Additional buffers must be provided if pipelined controls are to be partitioned for loading and timing. It can also be difficult to implement special control states, such as in response to a "stall" condition wherein the microprocessor must re-execute the previous instruction. If engineering changes are required to any of the logic functions, the design methodology does not permit accurate timing estimation until the changes are completely designed since delays through the circuits are dependent on the logical equations implemented. Finally, implementation of particularly complex functions usually requires full PLA structures. It would, therefore, be desirable to provide a method of generating control signals for a microprocessor which offered greater efficiency and flexibility than either conventional logic circuits or PLAs. It would be further advantageous if the method facilitated design changes in control signal generation without affecting timing estimation.